1. Technical Field
The present disclosure relates to a method for forming gate, source, and drain contacts on MOS transistor of nanometric dimensions.
2. Discussion of the Related Art
FIGS. 1 and 2 are cross-section views schematically illustrating successive steps of a method currently used to form gate, source, and drain contacts on MOS transistors.
FIG. 1 is a cross-section view schematically showing a portion of a semiconductor wafer on which MOS transistors have been formed.
The upper portion of a semiconductor wafer 1 has insulation regions 3, for example, trenches filled with an insulating material, extending therein. Insulating regions 3 delimit active areas 5 of wafer 1 where MOS transistors are formed. In FIG. 1, two MOS transistors having a common source/drain region are formed in a same active area. Each MOS transistor comprises a conductive gate 7 extending on wafer 1 and insulated therefrom by a gate insulator 9. Each gate 7 is surrounded with a spacer 11 made of an insulating material. Source and drain regions 13 extend in wafer 1 on either side of gates 7. Source and drain regions 13 and gates 7 are covered with a metal silicide 15, 16. Reference 15 designates the metal silicide, called gate silicide, covering gates 7, and reference 16 designates the metal silicide covering source and drain regions 13. An insulating material 17 has been deposited on wafer 1 to cover gates 7 coated with gate silicide 15.
FIG. 2 illustrates the structure after the forming of source, drain, and gate contacts on the MOS transistors. Insulating material 17 has first been leveled, for example, by a chem.-mech. polishing method. Openings 19 have then been formed in material 17, from the upper surface of material 17, to reach gate silicide 15 and metal silicide 16 covering source and drain regions 13. The openings providing access to gate silicide 15 are not shown in FIG. 2, since they are usually formed above gate portions covered with metal silicide located on insulating regions 3, outside of active area 5. To form openings 19, a mask has been used during a prior photolithography step to protect the areas of layer 17 which are not desired to be etched. Openings 19 have then been filled with a conductive material 21. Openings 19 filled with conductive material 21 form source, drain, and gate contacts 23 of the MOS transistors, where the gate contacts are not shown in the cross-section plane of FIG. 2.
Further, the sizes of MOS transistors, and especially their gate length Lg and spacing dg between the gates of two adjacent MOS transistors are continuously decreased.
For particularly small dimensions Lg and dg, for example, respectively on the order of 14 nm and on the order of 64 nm, it is difficult to properly align the mask defining openings 19 with respect to the source and drain regions and with respect to the gate. A misalignment of the contacts risks generating short-circuits between the source and drain regions and the gates of MOS transistors.
There is a need for a method for forming gate, source, and drain contacts on MOS transistors avoiding short-circuits between the source and drain regions and the gates of MOS transistors having a gate length smaller than 20 nm.